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CONFIDENTIAL
CY7C9536B
OC-48/STM-16 Framer with VC - POSIC2GVCTM
Features
* OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated * Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] * Complies with Bellcore GR253 rev.1, 1997
[3]
* PPP control packets optionally sent to host CPU interface * MAC/layer 3 address look up and tagging. * Programmable A1A2 processing bypass in Rx direction with frame sync input * Complete section overhead (SOH), line overhead (LOH), and path overhead (POH) processing * APS extraction, CPU interrupt generation, and programmable insertion of APS byte * Line side APS port interface * Provision for protection switching on SONET/SDH port * Programmable PRBS generator and receiver * Serial port to access line/section data communication channel (DCC) and voice communication channel (VCC) * Full duplex OIF-SPI (POS-PHY)/UTOPIA level 3 interface[14,15] * 16-bit/32-bit host CPU interface bus * JTAG and boundary scan * Glueless interface with Cypress CYS25G0101DX OC-48 PHY * 0.18-um CMOS, 504-pin BGA package * +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for HSTL/LVPECL I/O supply, and +0.75V/2.0V reference
* Channelized operation: supports 16xOC-3 and 4xOC-12 within OC-48 stream * Supports TUG3 mapping in SDH mode * Virtual concatenation enables secure and dedicated bandwidth provisioning[4] * Up to 16 channels * From 50-Mbps to 1.2-Gbps bandwidth per channel * STS-1 and STS-3c granularity * Full duplex mapping of ATM cells over SONET/SDH * Complies with ITU-Standards I 432.2[5,6,7] * Full duplex mapping of packet-over-SONET/SDH: IETF RFC 1619/1662/2615 (HDLC/PPP)[8,9,10] * Generic Framing Procedure (GFP) per ANSI T1X1.5[11,12,13] Protocol Encapsulator/Decapsulator delineates GFP frames with length-CRC frame construct * GFP 268r1 * User-programmable encapsulation * User-programmable clear channel transport * User-programmable SONET/SDH bypass * Programmable frame tagging engine for packet preclassification enables such features as * MPLS label lookup and tagging * PPP: LCP and NCP tagging
Applications
* Multi-service nodes * ATM switches and routers * Packet routers and multiservice routers * SONET/SDH/Add-Drop Mux for packet/data applications * SONET/SDH/ATM/POS test equipment
Notes: 1. ITU-T Recommendation G.707. "Network Node Interface for the Synchronous Digital Hierarchy." 1996. 2. ITU-T Recommendation G.783. "Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks." 2000. 3. Bellcore Publication GR-253-Core. "Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria." 1997. 4. Jones, N., Lucent Microelectronics, and C. Murton, Nortel Networks. "Extending PPP over SONET/DSH with Virtual Concatenation, High-Order and Low-Order payloads." Internet Draft. June 2000. 5. ITU-T Recommendation I.432.3. "B-ISDN User-Network Interface--Physical Layer Specification: 1544 kbit/s and 2048 kbit/s Operation." 1999. 6. American National Standards Institute. "Synchronous Optical Network (SONET)--Basic Description Including Multiplex Structure, Rates and Formats." ANSI T1.105-1995. 7. American National Standards Institute. "Synchronous Optical Network (SONET)--Payload Mappings." ANSI T1.105.02-1998. 8. Simpson, W. "PPP over SONET/SDH." RFC 1619. May 1994. 9. Simpson, W., ed. "PPP in HDLC-like Framing," RFC 1662. Daydreamer. July 1994. 10. Malis, A. and W. Simpson. "PPP over SONET/SDH," RFC 2615. June 1999. 11. Hernandez-Valencia, E., Lucent Technologies. "A Generic Frame Format for Data over SONET (DoS)." March 2000. 12. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999. 13. Hernandez-Valencia, E., Lucent Technologies. T1X1.5/2000-209. "Generic Framing Procedure (GFP) Specification." October 9-13, 2000. 14. ATM Forum, Technical Committee. UUTOPIA 3 Physical Layer Interface." Af-phy-0136.000. November 1999. 15. Can, R. and R. Tuck. "System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link-Layer Devices." OIF-SPI3-01.0. June 2000.
Cypress Semiconductor Corporation Document #: 38-02078 Rev. *G
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised April 25, 2005
CONFIDENTIAL
NoBL SRAM
CY7C9536B
E /O LAN, CBR, c lie n t p o r ts , e tc . L in k L a y e r D e v ic e fo r E th e r n e t, FC, DVB, A T M , e tc . SPI - 3 HBST U T O P IA P O S IC D e v ic e CYS25G 0101DX
O C -4 8
T r a n s c e iv e r O /E
CPU
Figure 1. POSIC2GVC System Application Diagram
POSIC2GVC Logic Block Diagram
TXD[31:0] TXCLKI TXCLKOUT TXFRAME_PULSE SONETTX_PAROUT TX SONET Line Interface POHSDIN TOHSDIN TE1STROBE TE2STROBE SONET Transmit SONET Framing Overhead Processor Bypass Pointer Processor Transmit SONET Text Framer RXD[31:0] RXCLK RXFRAME_PULSE RXCLKs SONETRX_PARIN LFI RX SONET Line Interface
Receive SONET Receiv e De-Framer SONET SONE Receive SONET Framing T Overhead Overhe Processor Bypass ad Pointer Insertio Processor n
Clk16MHz Clk2MHz POHSDOUT RPOHSTART TPOHSTART RE1STROBE RE2STROBE TOHSDOUR
VC TX (Virtual Concatenation)
VC RX (Virtual Concatenation)
TX ATM Encapsulator
TX HDLC Encapsulator
TX Generic Framing Procedure (GFP) Encapsulator
RX RX ATM HDLC Decapsulator Decapsulator
RX Generic Framing Procedure (GFP) Decapsulator
TCK TRST TDI TMS TDO General Pins
JTAG Interface
Programmable Frame Tagging
Transmit UTOPIA/SPI-3 Interface
CPU Interface
Receive UTOPIA/SPI-3 Interface
RST_n SYSCLK RSTOUT_n CLKOUT TEST[2:0] POSIC_OEN SCAN_ENA
TFCLK TERR TDAT[31:0] TPRTY TADD[3:0] TMOD[1:0] TSOP TEOP STPA PTCA TENB TSX DTCA[3:0]
CpuClk CpuTs_n/ CapuAds_n CpuSel CpuBlast_n CpuTa_n ChipSel CpuInt CpuClkFail CpuWrRd CpuAD[31:0] Mode
RVAL RENB RFCLK RDAT[31:0] RADD[7:0] RMOD[1:0] RPRTY RERR REOR RSOP RCA RSX
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CONFIDENTIAL
Overview
The CY7C9536B (POSIC2GVC) is a highly integrated SONET/SDH framer device for transport of ATM and IP packets over SONET/SDH links. It features special functions and architecture to support next-generation optical networking protocols for both SONET/SDH and direct data-over-fiber networks. OIF-SPI (POS-PHY) level 3, UTOPIA level 3 and High-Bandwidth Synchronous Transfer (HBST) interfaces are provided on the system side. POSIC2GVC performs complete SOH, LOH, and POH processing. Complete access to all overhead bytes is provided through register access via the host CPU interface. Access to selected overhead bytes are also available through serial port. Optional frame sync input and Transport Overhead (TOH) bypass enables better interface with STS-1 switched streams. The virtual concatenation feature, with up to 16 channels, enables provisioning of secure, dedicated and right-sized bandwidth for Ethernet or ATM transport. Up to 16 virtual channels can be created with STS-1 or STS-3c granularity. Bandwidth from 50 Mbps to 1.2 Gbps can be allocated per channel. POSIC2GVC supports packet over SONET/SDH as PPP in HDLC-like frame as per IETF rfc 1619/1662/2615 (PPP). POSIC2GVC also supports full duplex ATM over SONET/SDH transport in compliance with ITU I432.2. POSIC2GVC supports the new generation Generic Framing Procedure (GFP) protocol encapsulation/Decapsulation over SONET/SDH. This protocol engine features wire rate framing, frame delineation and deframing with length-CRC pair header construct. Optional payload scrambling/descrambling and payload FCS are also provided. Clear channel mode enables transport of any raw byte streams on selected virtual channels, while the rest of the channels are transporting data through any one of encapsulation/decapsulation engines. The Programmable Frame Tagging Engine enables wire rate tagging of packets/frames. For new generation networking features such as MPLS, this engine can be programmed to tag based on existence/lack of specific label/field values, in the first 64 bytes of each packet. This way, packets are tagged for a variety of conditions, all programmable by the user, enabling sorting of packets in the incoming data stream and buffering packets accordingly. In a PPP application, control packets can optionally be sent over the host CPU interface directly. SONET/SDH bypass mode allows use of this device for data transport in non SONET/SDH point-to-point and mesh optical networks.
CY7C9536B
or HBST operations. In these cases, the first data transfer always carry the channel number. POSIC2GVC supports three basic types of encapsulation, namely (i) ATM, (ii) HDLC frame, and (iii) GFP (frames with length-CRC pair header construct based delineation). Clear channel or transparent mode (no encapsulation) is also supported. While in operation, only one type of encapsulation can be enabled for all VC channels. Some or all of the VC channels can be programmed as clear channels. For Clear Channels, the encapsulator engine will bypass the encapsulation and pass the packets without any processing to the next block. Encapsulated packets are transferred to the Virtual Concatenation (VC) block along with the channel number. The VC block rearranges the packet/frame flow to support the bandwidth allocation for virtual channels. Bandwidth is assigned by allocating a programmed number of SPEs to each channel. The VC block keeps track of the SPE under construction by the SONET/SDH framer block and transfers the packets meant for a given channel to the SONET framer. Since POSIC2GVC does not have a packet storage memory on-chip, a channel bandwidth balanced packet flow is expected from the system side. To enable such a balanced transfer, POSIC2GVC has internal FIFO of 512 bytes per channel. The status of FIFO is provided through pins to the link layer. Finally, the SONET/SDH framer inserts the packet /cells into the SONET/SDH frame. All overhead bytes are added. All alarm bits and status bits are inserted based on the status of incoming frames as well as programming done by the host CPU. The scrambler meets relevant standards and can optionally be disabled. Frames are finally sent out on the fiber side interface. If programmed to do so, the SONET/SDH framer can be bypassed and encapsulated packets/frames can be sent directly to the fiber-side interface.
Receive
In the receive direction, SONET/SDH frames are received from the fiber side. Data packets/frames are extracted from the payload and passed onto the selected decapsulator engine after compensation for differential delay, in case of virtual concatenation. If the SONET/SDH framer is bypassed, the incoming data stream is directly passed over to the decapsulator engine. Data packets/frames are then decapsulated and sent to the Programmable Frame Tagging Engine. They are then analyzed and tagged before sent out to the system side via the OIF-SPI level 3, UTOPIA or HBST interface. Tagging of frames is optional. SONET/SDH frames entering from the fiber side are synchronized and the frame boundary is identified with A1A2 bytes. Frames can be optionally synchronized with Frame_Sync_Input to identify the boundary. Descrambling is performed to retrieve scrambled frames. Complete processing of all overhead bytes, Section, Line and Path, is performed and all alarm bits are verified and alarms are raised as programmed. Full access to all overhead bytes is provided through register access. Access to selected overhead bytes is also provided through serial bus. The SONET/SDH deframing can be entirely bypassed. The extracted payload is transferred to the VC block where it is reorganized to compensate for any differential delay encountered in the network from the virtual concatenation Page 3 of 46
Transmit
In the transmit direction, packets are received from the system side, encapsulated/framed and mapped into the SONET/SDH payload. Finally the TOH is added and SONET/SDH frames are passed onto the fiber side/line side interface on a parallel bus. The system side interface can be programmed either as OIF-SPI level 3, or UTOPIA level 3 or HBST modes. In the UTOPIA mode, ATM cells can be received either in 54- (8-bit interface) or 56- (8-bit and 32-bit interfaces) bytes format. The sixth byte carries the channel number of the cell. In case of packets, the interface can be programmed as OIF-SPI level 3 Document #: 38-02078 Rev. *G
CONFIDENTIAL
channel. For this purpose, up to 256 frames are stored in external memory. The VC block then passes the payload stream to the selected decapsulator engine. The selected decapsulator engine delineates the payload stream, decapsulates and extracts packets/cells from the stream. Descrambling of packets/cells is optional. The packets/cells are then sent out to the programmable Frame Tagging Engine. The Frame Tagging Engine optionally tags the packet/cell as programmed. The packet/cell is then transferred to the link layer device, through the System Interface (OIF-SPI/UTOPIA level 3, or HBST), with an additional eight bits of information. Four bits specify the VC channel and the other four bits specify the tag. VC-3-1v/STS-1-1v[17] VC-3-2v/STS-1-2v VC-3-3v/STS-1-3v VC-3-4v/STS-1-4v VC-3-5v/STS-1-5v VC-3-6v/STS-1-6v VC-3-7v/STS-1-7v VC-3-8v/STS-1-8v VC-4-1v/STS-3c-1v[17] VC-4-2v/STS-3c-2v VC-4-3v/STS-3c-3v VC-4-4v/STS-3c-4v VC-4-5v/STS-3c-5v VC-4-6v/STS-3c-6v VC-4-7v/STS-3c-7v VC-4-8v/STS-3c-8v VC-4-4c-1v/STS-12c-1v[17] VC-4-4c-2v/STS-12c-2v VC4-8c-1v/STS-24c-1v[17]
CY7C9536B
(~50 Mbps) (~100 Mbps) (~150 Mbps) (~200 Mbps) (~250 Mbps) (~300 Mbps) (~350 Mbps) (~400 Mbps) (~150 Mbps) (~300 Mbps) (~450 Mbps) (~600 Mbps) (~750 Mbps) (~900 Mbps) (~1.05 Gbps) (~1.2 Gbps) (~600 Mbps) (~1.2 Gbps) (~1.2Gbps)
Table 1. Virtual Concatenated Channel Bandwidth[16]
Virtual Concatenation
Virtual concatenation creates multiple virtual payloads of different sizes within the incoming SONET/SDH frame, effectively creating multiple channels of different bandwidth. The advantages of VC are: * Efficient and dedicated bandwidth allocation. * Compatibility with TDM access infrastructure. Virtually concatenated channels can coexist with aware and nonaware Network Elements on the same shared access. * Independence from upper layer data protocol/frame format. * Fine granularity channels are extensible and easily provisionable. POSIC2GVC supports VC for all types of packets/frames/ protocols it transports on SONET/SDH. Up to 16 channels can be created using STS1/VC-3, STS3c/VC-4, STS12c/VC4-4c and STS24c/VC4-8c. POSIC2GVC also supports non-virtually concatenated channels such as STS3c and STS12c. Table 1 shows a list of virtually concatenated channel bandwidth supported by POSIC2GVC. Virtual concatenation requires specific overhead processing capabilities only at the path terminating equipment. It remains transparent at the intermediate nodes in the network. It is possible therefore that two or more different SPEs, virtually bonded to create a channel, travel through different routes in the network. Hence, they can arrive at the destination in the order different from the order at the point of origination. Delay encountered in arrival of two virtually concatenated SPEs in a frame is called differential delay. To compensate for differential delay, the SPE received earlier need to be stored until the particular SPE, which is previous in the order but faces longer travel time, arrives at the terminating node. POSIC2GVC can store up to 256 SONET/SDH frames in external memory, which can compensate for 16 ms of differential delay. For differential delay higher than that, POSIC2GVC raises an alarm.
Notes: 16. All VC mode channel configurations require a SYSCLK frequency of 133.33 MHz. 17. Please refer to device manual for allowed combinations of Virtual Channels using STSX-1v/VCX-1v granularity.
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CONFIDENTIAL
(Gigabit 1Gb Ethernet) Packet SPI - 3 SPI - 3 1Gb CH Packet 2 (Gigabit Ethernet) P O S I C SONET Cloud P O S I C
CY7C9536B
CH 1
1Gb CH Packet 1
Link Layer
Link Layer
1Gb Packet CH (Gigabit 2 Ethernet) 300Mb (3x100 Mb Ethernet OR TDM in clear channel mode) CH 3
300Mb CH 3 (3x100 Mb Ethernet OR TDM in clear channel mode)
15 CH 1 3 SONET Cloud 1 2 n 16 16 CH 1 3 2 1 CH 2 (OC3 SPEs may arrive in different order. At receiveing end, POSIC stores the SPEs in external memory to re-arrange them in correct order.) 15 n CH 3 CH 3
CH 2
Figure 2. Explanation of Virtual Concatenation
Generic Frame Encapsulation/Decapsulation
POSIC2GVC supports a variety of protocols/packets/frames to transport over a SONET/SDH link. For clarity of reference, in this document, framing of packets/cells into these protocols is called "encapsulation," and the engine performing encapsulation is called an "encapsulator." Similarly, deframing is called "decapsulation," and the engine performing decapsulation is called a "decapsulator." Three different encapsulator and decapsulator engines are integrated into POSIC2GVC. The ATM encapsulator computes and adds the HEC field, scrambles the cells and passes on to the VC block. In case of underflow, ATM encapsulator also creates programmable idle cells. The ATM decapsulator checks for HEC and integrity of the cell. It descrambles the cells, isolates and discards idle cells and passes ATM cells to the Programmable Frame Tagging Engine.
HDLC encapsulator performs Asynchronous Control Character Mapping (ACCM), stuffing, flag sequence insertion and scrambling. Optionally, up to 16 bytes of header is inserted ahead of the packet while framing the packet. The host CPU can program this 16-byte header through register programing. Such programmable header insertion enables encapsulation of PPP, frame relay or other protocol. The HDLC decapsulator descrambles the incoming byte stream and searches the flag sequence. Upon finding the boundary, decapsulator performs destuffing and ACCM demapping before passing the packets to the Programmable Frame Tagging Engine. The Generic Framing Procedure (GFP) Encapsulator/Decapsulator supports delineation based on length-CRC pair header construct. In the transmit direction, it computes a 16-bit header CRC based on 2-byte length value received from the link layer device. The length and CRC fields are inserted as header of the frame ahead of the packet. Scrambling of the payload and 32-bit payload CRC computation and insertion are optional.
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Protocol/Frame Types
"Clear Channel Transport"
CY7C9536B
ATM Framer ATM Deframer HDLC Framer HDLC Deframer GFP Protocol Framer SONET/ SDH Deframer Virtual Concatenation GFP Protocol Deframer "Clear Channel Transport" 1) Only one framer/deframer active 2) Selected VC channels can be declared "clear channel transport" Frame Tagger SPI-3/ UTOPIA
SONET/ SDH Framer
Virtual Concatenation
SPI-3/ UTOPIA
Figure 3. Protocol Framers In the receive direction, GFP frames are delineated based on the length-CRC construct pair header, integrity verified, payload extracted, optionally descrambled and sent to the Programmable Frame Tagging Engine. Any selected VC channel can be programmed to become a `clear channel'. The encapsulator and decapsulator remain in transparent mode for the clear channel and data passes through without any modification. This feature can be used to transport any raw data streams on a portion of bandwidth while the rest of the bandwidth is utilized for protocol traffic. The following functions can be achieved with the help of the Programmable Frame Tagging Engine: * Incoming packet analysis to parse packets/frames/cells at wire speed. * User-programmable routing of control packets to CPU for processing. * Incoming frames tagged based on bits (such as congestion) in incoming packets. * User-programmable offset to locate Ethernet and other frames within DOS and other proprietary MAN networking protocols to allow MPLS processing.
Programmable Frame Tagging Engine
The Programmable Frame Tagging Engine provides preclassification of the packets/frames at the wire rate. This helps in utilizing the link layer device more efficiently. The Programmable Frame Tagging Engine enables the user to perform preclassification of all the incoming packets into one of the 16 possible categories. Since each channel can have up to 16 different categories, and up to 16 virtual concatenated channels are possible, this engine supports up to 256 different categories. For classification, two-pass comparison can be specified. For each comparison a field of up to six bytes can be selected within the first 64 bytes of the packet and compared with up to 16 programmed values. The comparison is on a bit by bit basis and any bit comparison can be masked with a user programmable mask register. A four-bit tag is attached to the cell/packet, based on the match. Host CPU can program these parameters through register programming. The following drawing demonstrates one possible combination of classification with the help of the Programmable Frame Tagging Engine.
SONET/SDH Bypass
POSIC2GVC supports the SONET/SDH framer/deframer bypass mode. Host CPU can program such bypass. In this mode, the data frames/packets, encapsulated by one of the encapsulators, will be transmitted transparently through VC and SONET/SDH blocks to the fiber side and vice versa.
System Interface
The system interface is programmable. For application in an ATM system, POSIC2GVC system interface can be programmed to be PHY side interface as per UTOPIA level 3 specifications. For variable length packets, POSIC2GVC system interface can be programmed to be OIF-SPI level 3. ATM cells can also be transferred over OIF-SPI level 3 bus. System interface can be programmed in HBST mode. In this case, a separate set of address pins are supported on the system side. This mode supports high-speed burst access.
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System Memory at Host System
Tag #0 Control Packets Data Tag #1
CY7C9536B
Tagging enables sorting of packets by Host System
Data Packets
POSIC
Data Packets not belonging to this Node Tag #2
Rx Processing
SPI-3 Interface
Data
SONET/SDH
........
Tag #n Data
TTL-expired and other discard packets Tag #13 Data Errored packets (CRC and Parity) Tag #14 Data Node-sourced packets to be sinked Data Tag #15
Figure 4. Frame Tagging Engine Data Sorting Diagram
CPU Interface
POSIC2GVC can interface with 16-bit or 32-bit CPU. The CPU interface can be pin configured to be compatible with Motorola or Intel bus interface. The CPU interface provides access to all registers of POSIC2GVC, collates all interrupt generated by various blocks and also supports control packet transfers.
Table 2. Configuration Options Bus Width 8 bits 8 bits 16 bits 16 bits 32 bits Clock Frequency 19.44 MHz 77.76 MHz 38.88 MHz 155.52 MHz 77.76 MHz Line Rate OC-3/STM-1 OC-12/STM-4 OC-12/STM-4 OC-48/STM-16 OC-48/STM-16
Line Interface
The line interface/fiber side interface is configurable as 8 bit, 16-bit or 32-bit depending on the clock frequency and data rate. The options shown in Table 2 are available.
Clock Source
The transmit clock can be programmed to be one of the following sources: * Received clock supplied by the PHY * External transmit clock source.
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APS Port
POSIC2GVC provides a 16-bit APS port for 1+1 protection. The support of a main and standby PHY interface connectivity allows several different APS implementation options using POSIC2GVC. Multi-Framer APS Implementation Two POSIC2GVC devices can be connected to two different transceivers, optics and fibers. POSIC2GVC enables protection switching with only one device being main and connected to link layer. The standby POSIC2GVC device is connected to the main POSIC2GVC device and it is controlled by host CPU. POSIC2GVC provides APS byte information to the host CPU. The host CPU is expected to take a protection switching decision and provide necessary instructions to both POSIC2GVC devices. In case of protection switching, in the transmit direction, the main POSIC2GVC will perform all other operations as programmed, except some of the line and section processing of SONET/SDH framing. The main POSIC2GVC device will then pass on the SPEs to the standby device through the APS port. The standby device will then perform the rest of the line and section processing and transport SONET/SDH frames over standby fiber. Similarly, in case of protection switched mode, on the receive side, the standby device will process some of the line and section overhead and transfer the frames to main device through the APS port. The main device will perform the rest of the processing in the receive side. Single Framer APS Implementation A main and slave PHY device can be interfaced directly to the main and APS ports of a single POSIC2GVC device. In this case, the main PHY is connected to the main line interface and the standby PHY is connected to the APS port.
RxS RxS RxM PHY STANDBY POSIC STANDBY
CY7C9536B
TxS
TxS
RxS RxM PHY MAIN RxM POSIC MAIN TxS TxM TxM LINK LAYER DEVICE
Working Channel Protection
Figure 5. POSIC2GVC APS Implementation using Two POSIC Devices In the POSIC2GVC transmit path, SONET/SDH data is bridged across the main and APS ports (per linear 1+1 APS requirements). When protection switching, POSIC2GVC can be programmed to switch line inputs from the main receive port to the APS receive port, or vice versa. This APS scheme provides solely optical/PHY link level protection.
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OSC
CY7C9536B
Main OC-48 PHY
REFCLK TXCLKI TXCLKO TXD[15:0] M TXCLKO TXCLKI TXD [15:0] RXD[15:0] RXCLK LFI LFI M SFF Optical Module
RXD[15:0] RXCLK
POSIC2GVC Standby PHY
REFCLK TXCLKO LFI TXCLKI TXD[31:16] TXD [15:0] RXD[15:0] RXCLK SFF Optical Module
RXD[31:16] RXCLKS
Figure 6. POSIC2GVC APS Implementation Using a Single POSIC Device
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Pin Configuration
CY7C9536B
CY7C9536B (POSIC2GVC) Bottom View TM
POSIC (CY7C9536) Pin Diagram Bottom View
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Pin Description
Signal Name RXFRAME_PULSE TXFRAME_PULSE RXD[31:0] RXCLK RXCLKs TXCLKOUT I/O I Pad Type HSTL/LVTTL /LVPECL HSTL/LVTTL /LVPECL HSTL/LVTTL /LVPECL HSTL/LVTTL /LVPECL Pins JTAG 1 1 32 1 1 1 N N N N N N Pin Description Line Interface Signals
CY7C9536B
Optional frame pulse input for line interface. Active HIGH. Frame pulse output for line interface. Active HIGH. 32-bit single ended receive data bus for SONET/SDH link. This bus can be configured as two 16-bit buses in APS operation. Receive clock input from the PHY device for line interface. Receive clock input from the Slave PHY device for SONET/SDH link to support APS. Transmit Clock to physical layer device for line interface. This will be RXCLK or the TXCLKI based on the clock selection in the SONET Tx block register. During loopback this is same as the RXCLK. Input transmit clock from physical layer device for line interface. 32-bit single ended transmit data bus for line interface. This bus can be configured as two 16-bit buses in APS operation. SONET Tx Parity Output. Can be ODD/EVEN parity, as programmed in the SONET/SDH Tx block register. SONET Rx Parity Input. Can be ODD/EVEN parity, as programmed in the SONET/SDH Rx block register. Line fault indicator. When LOW, this signal indicates that the PHY has detected Loss of Optical signal on the SONET/SDH link. TOH Serial Port Clock Output. TOHDout is clocked out on rising edge of this clock and TOHDin is latched-in with falling edge of this clock. The frequency is 2.048 MHz, derived from SysClk. POH Serial Port Clock Output. POHDout is clocked out on rising edge of this clock and POHDin is latched-in with falling edge of this clock. The frequency is 16.625 MHz, derived from SysClk Transmit E1 Strobe. Transmit TOH serial port data start indication. Active HIGH pulse generated once in every 125 ms. Indicates the first bit of E1 Byte. Transmit E2 Strobe. Active HIGH pulse generated once in every 125 ms. Indicates the first bit of E2 Byte. Transmit POH Serial Port Data Start Indication. Active HIGH pulse generated once in every 125 ms. Transport over head serial port data input. Path over head serial port data input. Receive E1 Strobe. Receive TOH serial port data start indication. Active HIGH pulse generated once in every 125 ms. Indicates that the POSIC2GVC expects the first bit of the first byte of E1 should accompany the next clock edge. MSB is transmitted first. Receive E2 Strobe. Active HIGH pulse generated once in every 125 ms. Indicates that the POSIC2GVC expects the first bit of the first byte of E2 should accompany the next clock edge. MSB is transmitted first. Receive POH Serial Port Data Start Indication. Active HIGH pulse generated once in every 125 ms. Indicates that the POSIC2GVC expects the first bit of the first byte of RPOH should accompany the next clock edge. Transport over head serial port data output. Page 11 of 46
O HSTL/LVTTL I I I
O HSTL/LVTTL
TXCLKI TXD[31:0] SONETTX_PAROU T SONETRX_PARIN LFI_n
I
HSTL/LVTTL /LVPECL
1 32 1 1 1
N N N N Y
O HSTL/LVTTL O HSTL/LVTTL I I HSTL/LVTTL /LVPECL LVTTL
Overhead Bytes Access--Serial Ports Clk2MHz O LVTTL 1 Y
Clk16MHz
O LVTTL
1
Y
TE1STROBE
O LVTTL
1
Y
TE2STROBE TPOHSTART TOHSDIN POHSDIN RE1STROBE
O LVTTL O LVTTL I I LVTTL LVTTL
1 1 1 1 1
Y Y Y Y Y
O LVTTL
RE2STROBE
O LVTTL
1
Y
RPOHSTART
O LVTTL
1
Y
TOHSDOUT
O LVTTL
1
Y
Document #: 38-02078 Rev. *G
CONFIDENTIAL
Pin Description (continued)
Signal Name POHSDOUT I/O Pad Type Pins JTAG 1 Y Pin Description Path over head serial port data output. O LVTTL
CY7C9536B
System Interface (OIF-SPI level 3/UTOPIA level 3/HBST) signals (in this section, POS = OIF - SPI Level 3, ATM = Utopia level 3 mode) RVAL O LVTTL 1 N POS: Receive Data Valid (RVAL) signal. RVAL indicates the validity of receive data signals. RVAL will transition LOW when receive FIFO is empty or at the end of a packet. When RVAL is HIGH, the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, and RERR signals are valid. When RVAL is LOW, the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, and RERR signals are invalid and must be disregarded. HBST: Receive Data Valid (RDVAL) signal. The RDATA, RBVAL, RSOP, REOP, RERR, and RADDR are valid when this signal is active. POS: Receive Read Enable (RENB) signal. The RENB signal is used to control the flow of data from the receive FIFOs. During data transfer, RVAL must be monitored as it will indicate if the RDAT[31:0], RPRTY, MOD[1:0], RSOP, REOP, RERR and RSX are valid. The system may deassert RENB at anytime if it is unable to accept data from POSIC2GVC. When RENB is sampled LOW by POSIC2GVC, a read is performed from the receive FIFO and the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals are updated on the following rising edge of RFCLK. When RENB is sampled HIGH by POSIC2GVC, a read is not performed and the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals will not updated. ATM: Enable data transfers (RxENb*) signal Enables port selection. HBST: Receive Data Ready (RREADY_n) signal Active LOW signal, indicates ready to accept data. The device will send valid data 2 clocks after the assertion of this signal. POS: Receive FIFO Write Clock (RFCLK). RFCLK is used to synchronize data transfer transactions between the LINK Layer device and the POSIC2GVC. RFCLK may cycle at a rate up to 100 MHz. ATM: Transfer/interface clock (RxClk) HBST: Receive Clock (RCLK). Max 104 MHz Receive Clock for level-3 operation. All signals are latched out on the rising edge of this clock.
RENB
I
LVTTL
1
N
RFCLK
I
LVTTL
1
N
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CONFIDENTIAL
Pin Description (continued)
Signal Name RDAT[31:0] I/O Pad Type Pins JTAG 32 N Pin Description O LVTTL
CY7C9536B
POS: Receive Packet Data Bus (RDAT[31:0]) The RDAT[31:0] bus carries the packet octets that are read from the receive FIFO and the in-band port address of the selected receive FIFO. RDAT[31:0] is considered valid only when RVAL is asserted. Given the defined data structure, bit 31 is received first and bit 0 is received last. ATM: Receive Cell Data Bus (RxData[31:0]) The RDAT[31:0] bus carries the Cell octets that are read from the receive FIFO. RDAT[31:0] is considered valid only when RENB is asserted. Given the defined data structure, bit 31 is received first and bit 0 is received last RDAT[31:0] is updated on the rising edge of RCLK. This bus is big-endian in format. HBST: Receive Data Bus (RDATA[31:0]) 32-bit Data Bus, the data is valid when RDVAL signal is active. HBST: Receive Port Address (RADDR[7:0]). When RDVAL signal is active, this address on this bus indicates port address in RADDR[3:0] and tag value in RADDR[7:4]. In single-channel mode all 8 bits will contain the tag value. RADDR is considered valid only when RDVAL is asserted POS: Receive Word Modulo (RMOD[1:0]) signal. RMOD[1:0] indicates the number of valid bytes of data in RDAT[31:0]. The RMOD bus should always be all zero, except during the last double-word transfer of a packet on RDAT[31:0]. When REOP is asserted, the number of valid packet data bytes on RDAT[31:0] is specified by RMOD[1:0] RMOD[1:0] = "00" RDAT[31:0] valid RMOD[1:0] = "01" RDAT[31:8] valid RMOD[1:0] = "10" RDAT[31:16] valid RMOD[1:0] = "11" RDAT[31:24] valid RMOD[1:0] is considered valid only when RVAL is asserted. In 16-bit mode, only RMOD[0] is valid. RMOD[0] = "1" RDAT[15:8] valid (16-bit mode) RMOD[0] = "0" RDAT[15:0] valid (16-bit mode) HBST: Receive Data Byte Valid (RBVAL[1:0]) signals. This indicates the number of bytes data bytes valid on the RDATA bus, 00 = 4 bytes valid, 11 = 1 byte valid. POS: Receive Parity (RPRTY) signal. The receive parity (RPRTY) signal indicates the parity calculated over the RDAT bus. RPRTY supports both odd and even parity. ATM: Receive Parity (RxPrty) signal. Data bus odd parity. HBST: Receive bus parity (RPARITY) signal. Receive bus parity, Even/Odd parity calculated on the data bus alone or on all the bus signals (RDATA, RADDR, RDVAL, RBVAL, RSOP, REOP, RERR).
RADD[7:0]
O LVTTL
8
N
RMOD[1:0]
O LVTTL
2
N
RPRTY
O LVTTL
1
N
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CONFIDENTIAL
Pin Description (continued)
Signal Name RERR I/O Pad Type Pins JTAG 1 N Pin Description O LVTTL
CY7C9536B
POS: Receive error indicator (RERR) signal. RERR is used to indicate that the current packet is aborted and should be discarded. RERR shall only be asserted when REOP is asserted. Conditions that can cause RERR to be set may be, but are not limited to, FIFO overflow, abort sequence detection and FCS error. RERR is considered valid only when RVAL is asserted. HBST: Receive error indicator (RERR) signal. A HIGH indicates the current packet or cell has error. POS: Receive End Of Packet (REOP) signal. REOP is used to delineate the packet boundaries on the RDAT bus. When REOP is HIGH, the end of the packet is present on the RDAT bus. REOP is required to be present at the end of every packet and is considered valid only when RVAL is asserted. HBST: End of Packet/cell (REOP) signal. A high indicates the end of packet or cell. POS: Receive Start of Packet (RSOP) signal. RSOP is used to delineate the packet boundaries on the RDAT bus. When RSOP is HIGH, the start of the packet is present on the RDAT bus. RSOP is required to be present at the start of every packet and is considered valid when RVAL is asserted. ATM: Receive start of cell (RxSOC). This signal marks the start of a cell structure on the RxData bus. The first word of the cell structure is present on the RxData[31:0] bus when RxSOC is HIGH. RxSOC is updated on the rising edge of RxClk. HBST: Receive Start of Packet/cell (RSOP) signal. A HIGH indicates start of packet or start of cell. ATM: UTOPIA Receive Cell Available (RxClav). RxClav will be asserted, whenever a minimum of 1 cell of data is available in the Receive FIFO. HBST: Receive FIFO available (RSTFA) signal. RSTFA indicates when data is available in the receive FIFO. RSTFA will be asserted, whenever receive FIFO has at least predefined number of bytes to be read (the number of bytes is user programmable). RSTFA is updated on the rising edge of RCLK. POS: Receive start of transfer signal. RSX indicates when the in-band port address is present on the RDAT bus. When RSX is HIGH and RVAL is LOW, the value of RDAT[7:0] is the address of the receive FIFO to be selected by POSIC2GVC. Subsequent data transfers on the RDAT bus will be from the port as specified by the in band address.
REOP
O LVTTL
1
N
RSOP/RSOC
O LVTTL
1
N
RCA
O LVTTL
1
N
RSX
O LVTTL
1
N
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CONFIDENTIAL
Pin Description (continued)
Signal Name TFCLK I/O I Pad Type LVTTL Pins JTAG 1 N Pin Description
CY7C9536B
POS: Transmit FIFO Write Clock (TFCLK). TFCLK is used to synchronize data transfer transactions between the LINK Layer device and POSIC2GVC. TFCLK may cycle at a rate up to 100 MHz. ATM: Transfer/interface clock (TxClk). HBST: Transmit Clock (TCLK). Max 104 MHz Transmit Clock for level-3 operation. All transmit signals are sampled on rising edge of the clock. POS: Transmit Error Indicator (TERR) signal. TERR is used to indicate that the current packet should be aborted. When TERR is set HIGH, the current packet is aborted. TERR should only be asserted when TEOP is asserted. HBST: Transmit Error Indicator (TERR) signal. A HIGH indicates the current packet or cell has error. POS: Transmit Write Enable (TENB) signal. The TENB signal is used to control the flow of data to the transmit FIFOs. When TENB is HIGH, the TDAT, TMOD, TSOP, TEOP, and TERR signals are invalid and are ignored by POSIC2GVC. The TSX signal is valid and is processed by POSIC2GVC when TENB is HIGH. When TENB is LOW, the TDAT, TMOD, TSOP, TEOP and TERR signals are valid and are processed by POSIC2GVC. Also, the TSX signal is ignored by POSIC2GVC when TENB is LOW. ATM: Transmit write enable (TxEnb*). This signal is an active LOW input which is used to initiate writes to the transmit FIFOs. When TxEnb* is sampled HIGH, the information sampled on the TxData, TxPrty, and TxSOC signals are invalid. When TxEnb* is sampled LOW, the information sampled on the TxData, TxPrty, and TxSOC signals are valid and are written into the transmit FIFO. TxEnb* is sampled on the rising edge of TxClk. HBST: Transmit Data Valid (TDVAL_n) signal. The TDVAL_n signal is used to control the flow of data to the transmit FIFOs. When TDVAL_n is HIGH, the TDATA, TBVAL, TSOP, TADDR, TSOP, TEOP, and TERR signals are valid and are processed by POSIC2GVC.
TERR
I
LVTTL
1
N
TENB
I
LVTTL
1
N
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CONFIDENTIAL
Pin Description (continued)
Signal Name TDAT[31:0] I/O I Pad Type Pins JTAG 32 N Pin Description
CY7C9536B
POS: Transmit Packet Data Bus (TDAT) bus. This bus carries the packet octets that are written to the selected transmit FIFO and the in-band port address to select the desired transmit FIFO. The TDAT bus is considered valid only when TENB is simultaneously asserted. Data is transmitted in big endian order on TDAT[31:0]. Given the defined data structure, bit 31 is transmitted first and bit 0 is transmitted last. ATM: Transmit Data Bus (TxData) bus. This data bus carries the ATM cell. Data on this bus is valid only if TxEnb* is HIGH. TxData[31:0] is three-stated if TxEnb* is LOW. TxData[31:0] is updated on the rising edge of TxClk. HBST: Transmit Data Bus (TDATA) bus. 32-bit Data bus. The data is valid when TDVAL_n signal is active. POS: Transmit bus parity (TPRTY) signal. The transmit parity (TPRTY) signal indicates the parity calculated over the TDAT bus. TPRTY is considered valid only when TENB is asserted. TPRTY is supported for both even and odd parity. ATM: Transmit bus parity (TxPrty). This signal indicates the parity on the TxData bus. A parity error is indicated by a status bit and a maskable interrupt. TxPrty is considered valid only when TxEnb* is simultaneously asserted. TxPrty is sampled on the rising edge of TxClk. HBST: Transmit bus parity (TPARITY) signal. Even/Odd parity calculated on the data bus alone or on all the bus signals (TDATA, TADDR, TDVAL_n, TBVAL, TSOP, TEOP, and TERR). POS: Transmit address bus (PTADR) bus. Address driven by Link layer to poll and select the appropriate POSIC2GVC channel (port). The value for the Transmit and Receive portions of a channel should be identical. Address 31 indicates a null port. ATM: Transmit address bus (TxAddr) bus. Address of POSIC2GVC channel being selected. HBST: Port Address (TADDR) bus. Address driven by the Link Layer to indicate the port address of current data transfer.
TPRTY
I
LVTTL
1
N
TADD[3:0]
I
LVTTL
4
N
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CONFIDENTIAL
Pin Description (continued)
Signal Name TMOD[1:0] I/O I Pad Type LVTTL Pins JTAG 2 N Pin Description
CY7C9536B
POS: Transmit Word Modulo (TMOD[1:0]) signal. TMOD[1:0] indicates the number of valid bytes of data in TDAT[31:0]. The TMOD bus should always be all zero, except during the last double-word transfer of a packet on TDAT[31:0]. When TEOP is asserted, the number of valid packet data bytes on TDAT[31:0] is specified by TMOD[1:0]. TMOD[1:0] = "00" TDAT[31:0] valid TMOD[1:0] = "01" TDAT[31:8] valid TMOD[1:0] = "10" TDAT[31:16] valid TMOD[1:0] = "11" TDAT[31:24] valid In 16-bit mode, only TMOD[0] is valid. TMOD[0] = "1" TDAT[15:8] valid (16-bit mode) TMOD[0] = "0" TDAT[15:0] valid (16-bit mode) HBST: Transmit byte valid (TBVAL[1:0]) signals. This indicates the number of bytes data bytes on the TDATA bus, 00 = 4 bytes valid, 11 = 1 byte valid. POS: Transmit Start of Packet (TSOP) signal. TSOP is used to delineate the packet boundaries on the TDAT bus. When TSOP is HIGH, the start of the packet is present on the TDAT bus. TSOP is required to be present at the beginning of every packet and is considered valid only when TENB is asserted. ATM: Transmit start of cell (TxSOC) signal. This signal marks the start of a cell structure on the TxData bus. TxSOC must be present for each cell. TxSOC is considered valid only when TxEnb* is simultaneously asserted. TxSOC is sampled on the rising edge of TxClk. HBST: Transmit Start of Packet (TSOP) signal. A high indicates the start of packet or start of cell. POS: Transmit End of Packet (TEOP) signal. TEOP is used to delineate the packet boundaries on the TDAT bus. When TEOP is HIGH, the end of the packet is present on the TDAT bus. TEOP is required to be present at the end of every packet and is considered valid only when TENB is asserted. HBST: Transmit End of Packet (TEOP) signal. A HIGH indicates the end of packet or end of cell. POS: Transmit Packet Available (DTPA) bus. This signal provides direct status indication the fill status of the transmit FIFO. Note that, regardless of what fill level TPA is set to indicate "full" at, the transmit packet processor can store 256 bytes of data. When DTPA transitions HIGH, it indicates that the transmit FIFO has enough room to store a configurable number of data bytes. This transition level is selected in the CPU programmable registers. When TPA transitions LOW, it indicates that the transmit FIFO is either full or near full as specified by the CPU programmable registers. DTPA is updated on the rising edge of TFCLK. HBST: Polled FIFO available Status (TFAST) bus. When the signal TSOFST is active, the status of channels 0,4,8,12 is given first followed by 1,5,9,13 and 2,6,10,14 and the last 3,7,11,15.
TSOP
I
LVTTL
1
N
TEOP
I
LVTTL
1
N
DTCA[3:0]
O LVTTL
4
N
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CONFIDENTIAL
Pin Description (continued)
Signal Name STPA I/O Pad Type Pins JTAG 1 N Pin Description O LVTTL
CY7C9536B
POS: Selected Channel Transmit Packet Available (STPA) signal. STPA transitions HIGH when a predefined minimum number of bytes are available in the selected transmit FIFO. Once HIGH, STPA indicates that transmit FIFO is not full. When STPA transitions LOW, it optionally indicates that transmit FIFO is full or near full (user programmable). STPA always provides status indication for the selected channel in order to avoid FIFO overflows while polling is performed. STPA is three-stated when TENB is deasserted in the previous cycle. STPA is also deasserted when either the null-port address (0x1F) or an address not matching the POSIC2GVC address is presented on the TADR[3:0] signals when TENB is sampled HIGH (has been de-asserted during the previous clock cycle). STPA is mandatory only if packet-level transfer mode is supported. It is not be driven in byte-level mode. ATM: There is no corresponding pin definition in ATM mode, however, this pin will output the same signal as STPA in POS mode HBST: FIFO Available Status (TSTFA) signal. FIFO available status of the selected port is reflected on this pin two clocks after detecting the port address when the TDVAL signal is active. POS: Polled-Port Transmit Packet Available (PTPA) signal. PTPA transitions HIGH when a predefined (user-programmable) minimum number of bytes are available in the polled transmit FIFO. Once HIGH, PTPA indicates that the transmit FIFO is not full. When PTPA transitions LOW, it optionally indicates that transmit FIFO is full or near full (user-programmable). PTPA allows polling the POSIC2GVC channel selected by TADR[3:0] when TENB is asserted. PTPA is driven by a POSIC2GVC when its address is polled by TADR[3:0]. POSIC2GVC will three-state PTPA when either the null-port address (0x1F) or an address not matching POSIC2GVC is provided on TADR[3:0]. PTPA is mandatory only if in packet-level transfer mode. It will not be driven in byte-level mode. ATM: UTOPIA Transmit Cell Available (TxClav) The TxClav signal indicates when a cell is available in the transmit FIFO for the port polled by TxAddr[3:0] when TxEnb* is asserted. When HIGH, TxClav indicates that the corresponding transmit FIFO is not full and a complete cell may be written. When TxClav goes LOW, it can be configured to indicate either that the corresponding transmit FIFO is near full or that the corresponding transmit FIFO is full. TxClav is three-stated when either the null-Port address (0x1F) or an address not matching the address space set is latched from the TxAddr[4:0] inputs when TxEnb* is HIGH. TxClav is updated on the rising edge of TxClk. HBST: FIFO Available status on TFAST bus (TSOFST) signal. Active HIGH pulse indicates the start of FIFO available status on TFAST bus. This signal is repeated once in every four clocks. POS: Transmit Start of Transfer (TSX) signal. TSX indicates inband port address on the TDAT bus. When TENB is HIGH and TSX is asserted (HIGH), the value of TADR[3:0] is the address of transmit FIFO selected. TSX is valid only when TENB is deasserted.
PTCA
O LVTTL
1
N
TSX
I
LVTTL
1
N
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CONFIDENTIAL
Pin Description (continued)
Signal Name AD [18:0] I/O Pad Type Pins JTAG 19 N Pin Description Memory Interface for Virtual Concatenation O LVTTL
CY7C9536B
Synchronous Address Inputs Used to address up to six 512k x 36 NoBLTM SRAMs. Sampled at the rising edge of the CLK. Synchronous Write Enable Input, active LOW. This must be sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence Synchronous Advance/Load Input This pin is used to advance the on-chip (SRAM's) address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter of SRAM is advanced. When LOW, a new address is loaded into the SRAM for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Synchronous Chip Enable 1, active LOW. Sampled on the rising edge of CLK. Used to select/deselect first bank of the NoBL memory. Synchronous Chip Enable 2, active LOW. Sampled on the rising edge of CLK. Used to select/deselect second bank of the NoBL memory. Synchronous Chip Enable 3, active LOW. Sampled on the rising edge of CLK. Used to select/deselect third bank of the NoBL memory. Asynchronous Output Enable, permanently active LOW. This pin is internally grounded to the VSS2 bus. The pin should be connected to the OEN input of the NoBL memories, or alternatively, left unconnected if the NoBL OEN input is directly grounded on the board. Synchronous Bidirectional Data I/O lines for SRAM1. As inputs to SRAM, these pins feed into a data register that is triggered by the rising edge of CLK. As outputs from SRAM, they deliver the data contained in the memory location specified by A [18:0] during the previous clock rise of the read cycle. When OE is asserted LOW, the pins can behave as outputs from SRAM. When HIGH, DQ1 [31:0] are placed in a three-state condition by the SRAM. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Synchronous Bidirectional Data I/O lines for SRAM2. As inputs to SRAM, these pins feed into a data register that is triggered by the rising edge of CLK. As outputs from SRAM, they deliver the data contained in the memory location specified by A [18:0] during the previous clock rise of the read cycle. When OE is asserted LOW, the pins can behave as outputs from SRAM. When HIGH, DQ2 [31:0] are placed in a three-state condition by the SRAM. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. CPU Clock. Used to select between Intel and Motorola CPU. `0' = Motorola, `1' = Intel Transfer Start. Active LOW Write/Read Signal. In Intel mode, active HIGH for write operation. In Motorola mode, active LOW for write operation.
WE
O LVTTL
1
N
ADV/LD
O LVTTL
1
N
CE1
O LVTTL
1
N
CE2
O LVTTL
1
N
CE3
O LVTTL
1
N
OE
O LVTTL
1
N
DQ1[31:0]
I/O LVTTL
32
N
DQ2 [31:0]
I/O LVTTL
32
N
CPU Interface Signals CpuClk CpuSel CpuTs_n/CpuAds_n CpuWrRd I I I I LVTTL LVTTL LVTTL LVTTL 1 1 1 1 Y Y Y Y
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CONFIDENTIAL
Pin Description (continued)
Signal Name CpuTa_n CpuBlast_n / CpuBdip_n CpuInt/ CpuClkFail CpuAD[31:0] ChipSel Mode TCK TRST TDI TMS TDO I/O I Pad Type LVTTL Pins JTAG 1 1 1 1 32 1 1 1 1 1 1 1 Y Y Y Y Y Y Y Pin Description O LVTTL
CY7C9536B
Transfer Acknowledge/Data Ready. Active low. Open Drain Output Used with Burst Transaction. Active LOW. Interrupt to CPU. Active LOW. CPU Clock Fail Signal. When LOW indicates failure of CPU clock. Address/Data Bus. The chip select signal for POSIC2GVC. Active Low. 32-/16-bit mode select. `0' = 32-bit mode, `1' otherwise. JTAG Mode: Test clock JTAG Mode: Test reset JTAG Mode: Test input JTAG Mode: Test mode Select. Pull-down to GND during normal operation. JTAG Mode: Test Output
O LVTTL O LVTTL I/O LVTTL I I I I I I LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
JTAG Interface Signals
O LVTTL
Miscellaneous Signals VREF RST_n SYSCLK CLKOUT RSTOUT_n TEST[2:0] SCAN_ENA POSIC_OEN I I I VREF LVTTL LVTTL 4 1 1 1 1 3 1 1 N Y N N Y Y Y Y Reference Voltage for HSTL and LVPECL inputs. Set to GND during LVTTL mode of operation. Active LOW asynchronous reset input. 133-MHz System Clock. SYSCLK Out. Used as CLK for the Virtual Concatenation memories Reset Out, active low. Test Mode selection signals. Pull-up to `1' during normal operation. SCAN ENABLE pin. Active High. Pull-down to `0' for normal operation The POSIC2GVC Output Enable (POSIC_OEN) signal. When set to logic one, all POSIC2GVC outputs (except CpuTa_n and CLKOUT) are held three-state. When POSIC_OEN is set to logic zero, all interfaces are enabled. Pull-down to `0' for normal operation.
O LVTTL O LVTTL I I I LVTTL LVTTL LVTTL
Total IO Pins Power: VCC Pad+Core Power: GND Pad+Core TOTAL P P
336 85 83 504 I/Os: 336; Power: 168
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Pin Assignment Pin Assignment Table
Signal RDAT<0> RDAT<1> RDAT<10> RDAT<11> RDAT<12> RDAT<13> RDAT<14> RDAT<15> RDAT<16> RDAT<17> RDAT<18> RDAT<19> RDAT<2> RDAT<20> RDAT<21> RDAT<22> RDAT<23> RDAT<24> RDAT<25> RDAT<26> RDAT<27> RDAT<28> RDAT<29> RDAT<3> RDAT<30> RDAT<31> RDAT<4> RDAT<5> RDAT<6> RDAT<7> RDAT<8> RDAT<9> RADD<0> RADD<1> RADD<2> RADD<3> RADD<4> RADD<5> RADD<6> RADD<7> RERR RMOD<0> RMOD<1> RPRTY REOP RCA Document #: 38-02078 Rev. *G Ball F3 F2 J6 J5 J4 J3 J2 K5 K4 K3 K2 L5 G6 L4 L3 L2 L1 M5 M4 M3 M2 M1 N5 G5 N4 N3 G3 G2 H6 H5 H4 H2 N2 N1 P5 P4 P3 P2 R5 R4 T4 R2 R3 T5 T2 U4
CY7C9536B
Pin Type LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT Page 21 of 46
CONFIDENTIAL
Pin Assignment Table (continued)
Signal RSOP/RSOC RSX RVAL RFCLK RENB TADD<0> TADD<1> TADD<2> TADD<3> TDAT<0> TDAT<1> TDAT<10> TDAT<11> TDAT<12> TDAT<13> TDAT<14> TDAT<15> TDAT<16> TDAT<17> TDAT<18> TDAT<19> TDAT<2> TDAT<20> TDAT<21> TDAT<22> TDAT<23> TDAT<24> TDAT<25> TDAT<26> TDAT<27> TDAT<28> TDAT<29> TDAT<3> TDAT<30> TDAT<31> TDAT<4> TDAT<5> TDAT<6> TDAT<7> TDAT<8> TDAT<9> TERR TENB TPRTY TSOP TEOP TSX Ball T3 U5 U1 V3 U2 AE3 AE4 AF3 AG4 U3 V1 Y2 Y3 Y4 Y5 AA2 AA3 AA4 AA5 AA6 AB2 V2 AB3 AB4 AB6 AC2 AC3 AC4 AC5 AC6 AD2 AD4 V4 AD5 AE2 V5 W1 W2 W3 W4 W5 AF5 AE6 AG5 AF6 AD7 AG6
CY7C9536B
Pin Type LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Pin Assignment Table (continued)
Signal TFCLK TMOD<0> TMOD<1> DTCA<0> DTCA<1> DTCA<2> DTCA<3> STPA PTCA CPUTA_N CPUCLKFAIL CPUINT CPUAD<0> CPUAD<1> CPUAD<10> CPUAD<11> CPUAD<12> CPUAD<13> CPUAD<14> CPUAD<15> CPUAD<16> CPUAD<17> CPUAD<18> CPUAD<19> CPUAD<2> CPUAD<20> CPUAD<21> CPUAD<22> CPUAD<23> CPUAD<24> CPUAD<25> CPUAD<26> CPUAD<27> CPUAD<28> CPUAD<29> CPUAD<3> CPUAD<30> CPUAD<31> CPUAD<4> CPUAD<5> CPUAD<6> CPUAD<7> CPUAD<8> CPUAD<9> CPUSEL MODE CPUTS_N Ball AE7 AF7 AD8 AH6 AE8 AG7 AH7 AD9 AG8 AE9 AH8 AF9 AG9 AH9 AJ11 AE12 AF12 AH12 AE13 AF13 AG13 AH13 AJ13 AE14 AE10 AF14 AG14 AE15 AF15 AG15 AH15 AE16 AF16 AH16 AE17 AF10 AF18 AG18 AG10 AH10 AE11 AF11 AG11 AH11 AG16 AE18 AJ17
CY7C9536B
Pin Type LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT Open Drain Output LVTTL_OUT LVTTL_OUT LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IN LVTTL_IN LVTTL_IN
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CONFIDENTIAL
Pin Assignment Table (continued)
Signal CPUWRD CPUBLAST_N CHIPSEL SCAN_ENA POSIC_OEN CPUCLK RST_N TEST<0> TEST<1> TEST<2> TCK SYSCLK TDI TMS TRST TDO RSTOUT_N CLKOUT TOHSDIN POHSDIN TE1STROBE TE2STROBE TPOHSTART RPOHSTART CLK2MHz CLK16MHz RE1STROBE RE2STROBE POHSDOUT TOHSDOUT TXFRAME_PULSE SONETTx_PAROUT TXD<0> TXD<1> TXD<10> TXD<11> TXD<12> TXD<13> TXD<14> TXD<15> TXD<16> TXD<17> TXD<18> TXD<19> TXD<2> TXD<20> TXD<21> Ball AG19 AH17 AF19 AG17 AE19 AF20 AH18 AE20 AG21 AH19 AF21 AE21 AG20 AD21 AF22 AD22 AG23 C16 AE22 AG22 AH24 AF23 AH25 AD23 AF24 AE24 AF25 AG25 AE26 AG26 AE27 AD25 AD28 AD27 AB26 AB25 AB24 AA28 AA27 AA26 AA25 AA24 Y29 Y28 AD26 Y27 W27
CY7C9536B
Pin Type LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_IN LVTTL_IN LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT
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CONFIDENTIAL
Pin Assignment Table (continued)
Signal TXD<22> TXD<23> TXD<24> TXD<25> TXD<26> TXD<27> TXD<28> TXD<29> TXD<3> TXD<30> TXD<31> TXD<4> TXD<5> TXD<6> TXD<7> TXD<8> TXD<9> TXCLKOUT TXCLKI VREF VREF VREF VREF RXCLK RXCLKS RXD<0> RXD<1> RXD<10> RXD<11> RXD<12> RXD<13> RXD<14> RXD<15> RXD<16> RXD<17> RXD<18> RXD<19> RXD<2> RXD<20> RXD<21> RXD<22> RXD<23> RXD<24> RXD<25> RXD<26> RXD<27> RXD<28> Ball W26 W25 V28 V27 V26 V25 U29 U28 AC28 T28 T27 AC27 AC26 AC25 AC24 AB28 AB27 W28 R27 U27 P26 M25 G27 N28 H26 H27 H28 K29 L25 L26 L27 L28 M26 M27 M28 N25 N26 J24 N27 N29 P25 P27 P28 R25 R26 R28 T25
CY7C9536B
Pin Type HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTLLVPECL_IN 0.75V/2.0V INPUT 0.75V/2.0V INPUT 0.75V/2.0V INPUT 0.75V/2.0V INPUT HSTL/LVTT/LLVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN
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CONFIDENTIAL
Pin Assignment Table (continued)
Signal RXD<29> RXD<3> RXD<30> RXD<31> RXD<4> RXD<5> RXD<6> RXD<7> RXD<8> RXD<9> SONETRx_PARIN LFI_n RXFRAME_PULSE DQ1<0> DQ1<1> DQ1<10> DQ1<11> DQ1<12> DQ1<13> DQ1<14> DQ1<15> DQ1<16> DQ1<17> DQ1<18> DQ1<19> DQ1<2> DQ1<20> DQ1<21> DQ1<22> DQ1<23> DQ1<24> DQ1<25> DQ1<26> DQ1<27> DQ1<28> DQ1<29> DQ1<3> DQ1<30> DQ1<31> DQ1<4> DQ1<5> DQ1<6> DQ1<7> DQ1<8> DQ1<9> CE1 CE2 Ball T26 J25 U25 U26 J26 J27 J28 K25 K26 K28 H25 H24 F27 E27 D27 D24 C24 B24 F23 D23 C23 B23 F22 E22 C22 G26 F21 E21 D21 C21 B21 E20 C20 B20 E19 B19 F26 B18 A18 E26 F25 D25 C25 G24 E24 B17 D19
CY7C9536B
Pin Type HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN LVTTL_IN HSTL/LVTTL/LVPECL_IN LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_OUT LVTTL_OUT
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CONFIDENTIAL
Pin Assignment Table (continued)
Signal CE3 WE OE ADV/LD AD<0> AD<1> AD<10> AD<11> AD<12> AD<13> AD<14> AD<15> AD<16> AD<17> AD<18> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> AD<8> AD<9> DQ2<0> DQ2<1> DQ2<10> DQ2<11> DQ2<12> DQ2<13> DQ2<14> DQ2<15> DQ2<16> DQ2<17> DQ2<18> DQ2<19> DQ2<2> DQ2<20> DQ2<21> DQ2<22> DQ2<23> DQ2<24> DQ2<25> DQ2<26> DQ2<27> DQ2<28> DQ2<29> DQ2<3> Ball A17 B16 D18 C15 D17 C17 D13 C13 A13 D12 C12 B12 A12 C11 B11 E16 D16 E15 D15 E14 C14 B14 E13 E12 E11 C9 B9 F8 E8 C8 B8 F7 E7 D7 C7 D11 B7 E6 D6 C6 F5 D5 C5 F4 C4 E3 E10
CY7C9536B
Pin Type LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO
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CONFIDENTIAL
Pin Assignment Table (continued)
Signal DQ2<30> DQ2<31> DQ2<4> DQ2<5> DQ2<6> DQ2<7> DQ2<8> DQ2<9> VSS1 Ball E2 D2 D10 C10 B10 F9 E9 D9 A1, B1, AE1, AJ1, AJ2, AG12, A2, D3, AD3, AH4, AJ4, A4, AH5, AH14, C18, AJ18, AJ19, AH20, AH21, B22, AH23, AG24, B25, AH26, B27, K27, AJ28, AF28, A28, D28, F28, A29, B29, J29, M29, P29, AJ29 G1, J1, P1, T1, AA1, AC1, B2, C3, AJ3, E4, G4, A6, B6, AJ7, AF8, A9, AJ9, A11, AJ12, B13, AJ14, A16, AJ16, E17, C19, A20, AJ21, AJ22, A23, AE23, AJ23, A25, A27, AF27, AJ27, AH28, C29, D29, F29, R29, W29, AC29, AE29, AF29, AH29, Y25 D1, AF1, AG2, C2, B3, AH3, D4, AF4, B5, E5, AJ5, D20, D22, E25, A26, C26, D26, AF26, AJ26, AH27, AE28, E29, G29, H29, L29 AD1, AG1, AH1, AF2, AH2, AG3, B4, AB5, AE5, A7, A10, A14, AF17, A21, A22, AH22, C28, E28, G28 C1, E1, F1, H1, K1, R1, Y1, AB1, A3, H3, A5, AJ6, A8, D8, AJ8, AJ10, D14, A15, B15, AJ15, E18, A19, AJ20, E23, A24, AJ24, G25, AJ25, B26, C27, AG27, B28, AG29 AE25, AG28, T29, V29, AA29, AB29, AD29, Y26
CY7C9536B
Pin Type LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO Core + Input Pin GND
VSS2
Output Pin GND
VCC1 VCC2 VCC3
Core Voltage, 1.8V
LVTTL Input Pin Power Supply, 3.3V
LVTTL Output Pin Power Supply, 3.3V
VCC5
HSTL Output Pin Power Supply, 1.5V/3.3V
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CONFIDENTIAL
Maximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.) Operating range specifies temperature and voltage boundary conditions for safe operation of the device. Operation outside these boundary may affect the performance and life of the device. Table 3. Device Absolute Maximum Ratings Parameter Case Temperature Storage Temperature Absolute Maximum Junction Temperature Lead Temperature Supply Voltage VCC1 for Core Supply Voltage VCC2 for LVTTL Inputs Supply Voltage VCC3 for LVTTL Outputs Supply Voltage VCC5 for HSTL/LVTTL Outputs VREF All Inputs Values Static Discharge Voltage (ESD) from JESD22-A114 Latch-up Current Maximum output short circuit current for all I/O configurations. (Vout = 0V)[18] Value -40 to 85 150 125 220 2.43 4.785 4.785 4.785 VCC + 0.3 VCC + 0.3 >2000 >200 -100
CY7C9536B
Unit C C C C V V V V V V V mA mA
Operating Range
Table 4. Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC1 1.71V to 1.89V 1.71V to 1.89V VCC5(HSTL) 1.425V to 1.575V 1.425V to 1.575V VCC2, VCC3, VCC5 3.135V to 3.465V 3.135V to 3.465V
DC Specifications
Table 5. DC Specifications Parameter VCC1 VCC2 VCC3 VCC5 VREF(HSTL) VREF(LVPECL) ICC1 ICC2 ICC3 ICC5 PW[19] Description Power Supply for Core Power Supply for LVTTL Inputs Power Supply for LVTTL Outputs Power Supply for HSTL/LVTTL Outputs Reference voltage for HSTLinputs Reference voltage for LVPECL inputs VCC1 Supply Current VCC2 Supply Current VCC3 Supply Current VCC5 Supply Current for LVTTL Output VCC5 Supply Current for HSTL Output Total Chip Power 20-pF capacitive load 20-pF capacitive load 20-pF capacitive load 20-pF capacitive load Test Conditions Min. 1.71 3.135 3.135 1.425/3.135 0.68 VCC2 - 1.4 - - - - - Max. 1.89 3.465 3.465 1.575/3.465 0.9 VCC2 - 1.2 1 0.1 0.75 0.28 0.017 4.58 Unit V V V V V V A A A A A Watt
Note: 18. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. Tested initially and after any design or process changes that may affect these parameters. 19. Consult factory for Power Consumption with external termination resistors.
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CONFIDENTIAL
Table 5. DC Specifications (continued) Parameter IOS[20] LVTTL I/Os VOHT VOLT VIHT VILT IIHT IILT HSTL I/Os VREF VOH(DC) VOL(DC) VOH(AC) VOL(AC) VIH(DC) VIL(DC) VIH(AC) VIL(AC) IIHH IILH LVPECL Inputs VREF VIH(DC) VIL(DC) VIH(AC) VIL(AC) IIHH IILH Reference Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current All VCC = Max. VIN = VCC2 All VCC = Max. VIN = 0V VCC2 - 1.4 VCC2 - 1.1 - VCC2 - 1.0 - - - Reference Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VCC1 = 1.71V VCC1 = 1.89V All VCC = Max. VIN = VCC1 All VCC = Max. VIN = 0V All VCC = Min. IOH = -8.0 mA All VCC = Min. IOL = 8.0 mA 0.68 VCC5 - 0.4 - VCC5 - 0.5 - VREF + 0.1 - VREF + 0.2 - - - Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current All VCC = Max., VIN = VCC2 All VCC = Max., VIN = 0V All VCC = Min. IOH = -8.0 mA All VCC = Min. IOL = 8.0 mA 2.4 2.0 -0.3 - - Description Output Short Circuit Current for all I/O configurations. See note below. Test Conditions VOUT = 0V Min. -20
CY7C9536B
Max. -100 Unit mA
- 0.4 VCC2 + 0.3 0.8 10 -10 0.9 - 0.4
V V V V A A
V V V
0.5 VREF - 0.1 VREF - 0.2 10 -10
V V V V V A A
VCC2 - 1.2 - VCC2 - 1.5 VCC2 - 1.6 10 -10
V V V V V A A
Note: 20. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. Tested initially and after any design or process changes that may affect these parameters.
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CONFIDENTIAL
AC Test Loads and Waveform
3.0V Vth= 1.4V GND < 1ns
1.4V
CY7C9536B
2.0V 0.8V
2.0V 0.8V
Vth= 1.4V < 1ns
Output
50 ohm T-line
CL
.
R1
Test Point R1=125 ohm CL < 20pF
(a) LvTTL Input Test Waveform
(a) LVTTL AC Test Load
1.5V
50 ohm T-line
VIHH Vth= 0.75V VIHL < 1ns
80% 20%
80% 20%
Vth= 0.75V < 1ns
Output
CL
.
R1
Test Point
R2
R1=100 ohm R2=100 ohm CL < 12pF
(b) HSTL Input Test Waveform
(b) HSTL AC Test Load
3.3V
Test Point
VIH Vth= 2.0V VIL < 1ns
80% 20%
80% 20%
R1
Vth= 2.0V < 1ns
50 ohm T-line
R2 R3
Output
R1=125 ohm R2=79 ohm R3=138 ohm CL C = 7pf L
(c) LVPECL Input Test Waveform
(c) LVPECL-compliant Termination
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CONFIDENTIAL
Reset Requirements
Asserting the RST_n signal will asynchronously reset all sequential elements of POSIC2GVC. Even though the reset is treated as asynchronous signal, it is recommended that a minimum of 1-ms-wide active LOW RST_n is applied after all power supplies have stabilized.
CY7C9536B
There is no particular power-up sequence requirements among VCC1, VCC2, and VCC3 in this case. There is no particular power-up sequence requirements among VCC1, VCC2, VCC3, and VCC5 if HSTL I/O is not used. RST_n needs to be activated until all the power supplies have stabilized.
Power-Up Requirements
When HSTL I/O is used, VCC1, VCC2, and VCC3 need to be powered up first before VCC5 supply. VCC5 shall be powered up at least 300ms after the last of the other power supplies. Table 6. POSIC2GVC Pin Timing Requirements POSIC2GVC Pin Group Line Interface Peripheral Device/Bus Standard 16-/8-bit HSTL/single-ended LVPECL interface LVTTL
AC and Timing Specifications
The POSIC2GVC device interfaces to industry standard peripheral devices or buses. Hence the POSIC2GVC pin timing parameters are governed by the interface requirements of the peripherals or the relevant standards. Table 6 details the timing requirements.
Compatible/Suggested Part Number Reference/Remarks CYS25G0101DX Refer PHY data sheet Described in this document CY7C1370B/C or CY7C1464V33 (min. 200-MHz grade) Compatible to NoBLTM or equivalent memory chip ATM Forum: BTD-PHY-UL3-01.05 Saturn Group: PMC-980495 Issue Described in this document Compatible with Intel/Motorola CPUs
Overhead Bytes Access - Serial Ports Memory Interface LVTTL
System Interface
Host CPU Interface
UTOPIA Level 3/ OIF-SPI Level3 HBST 16-/32-bit CPU Interface LVTTL
AC Specifications
Table 7. Line Interface Timing Parameter Values Parameter fTS[21] Description TXCLKOUT, TXCLKI Frequency (must be frequency coherent to RXCLK when used as the transmit PLL clock source). fTS nominal (fTSN) can be 155.52 MHz, 77.76 MHz, 38.88 MHz, 19.44 MHz; depends on the Bus Width and Line Rate used. TXCLKI Period TXCLKI Duty Cycle TXCLKOUT Period TXCLKOUT Duty Cycle TXCLKOUT Rise Time TXCLKOUT Fall Time TXD Output Delay after of TXCLKOUT TXFRAME_PULSE Output Delay after of TXCLKOUT SONETTX_PAROUT Output Delay after of TXCLKOUT TXFRAME_PULSE Width RXCLK Frequency fRS nominal (fRSN) can be 155.52 MHz, 77.76 MHz, 38.88 MHz, 19.44 MHz; depends on the Bus Width and Line Rate used. RXCLK Period Min. fTSN * (1 - 0.65%) Max. fTSN * (1 + 0.65%) Unit MHz
tTXCLKIP[21] tTXCLKID tTXCLKP[21]
1/(fTS max.) 43 1/(fTS max.) 40 0.3 0.3 0.5 0.5 0.5 6 fRSN * (1 - 0.65%) 1/(fRS max.) 43 -
1/(fTS min.) 57 1/(fTS min.) 60 1.5 1.5 4.5 4.5 4.5 55 fRSN * (1 + 0.65%) 1/(fRS min.) 57 1.5
ns % ns % ns ns ns ns ns ns MHz
tTXCLKD[21] tTXCLKR[22] tTXCLKF[22] tTXDO tTXFPO tPAROUTO tTXFPPW fRS[21]
tRXCLKP[21]
ns % ns
RXCLK Duty Cycle tRXCLKOD[21] RXCLK Rise Time tRXCLKR[22] Notes: 21. The parameter is guaranteed by design and is not tested during production. 22. The parameter is guaranteed by characterization and is not tested during production. Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Table 7. Line Interface Timing Parameter Values (continued) Parameter tRXCLKF[22] tRXDS tRXDH tRXFPS tRXFPH tPARINS tPARINH RXCLK Fall Time Recovered Data Set-up to of RXCLK Recovered Data Hold from of RXCLK RXFRAME_PULSE Set-up to of RXCLK RXFRAME_PULSE Hold from of RXCLK SONETRX_PARIN Set-up to of RXCLK SONETRX_PARIN Hold from of RXCLK Description Min. - 1.5 1.25 1.5 1.25 1.5 1.25
CY7C9536B
Max. 1.5 - - - - - - Unit ns ns ns ns ns ns ns
Table 8. OIF-SPI Level 3 Transmit System Interface Timing Parameter Values Parameter tTFCLKD[21] tTENBS tTENBH tTDATS tTDATH tTPRTYS tTPRTYH tTSOPS tTSOPH tTEOPS tTEOPH tTERRS tTERRH tTSXS tTSXH tTMODS tTMODH tPTADRS tPTADRH tDTPAO tSTPAO tPTCAO fTFCLK
[21]
Description TFCLK Frequency TFCLK Duty Cycle TENB Set-up time to TFCLK[23] TENB Hold time to TFCLK[24] TDAT[31:0] Set-up time to TFCLK[23] TDAT[31:0] Hold time to TFCLK[24] TPRTY Set-up time to TFCLK[23] TPRTY Hold time to TFCLK[24] TSOP Set-up time to TFCLK[23] TSOP Hold time to TFCLK[24] TEOP Set-up time to TFCLK[23] TEOP Hold time to TFCLK[24] TERR Set-up time to TSX Set-up time to TFCLK[23] TERR Hold time to TFCLK[24] TFCLK[23] TFCLK[23]
[23]
Min. 40 2 0.5 2 0.5 2 0.5 2 0.5 2 0.5 2 0.5 2 0.5 2 0.5 2 0.5 1.5 1.5 1.5
Max. 104 60 - - - - - - - - - - - - - - - - - - 6 6 6
Unit MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TSX Hold time to TFCLK[24] TMOD Set-up time to TMOD Hold time to TFCLK[24] PTADR Set-up time to TFCLK PTADR Hold time to TFCLK[24] TFCLK HIGH to DTPA Valid[25, 26] TFCLK HIGH to STPA Valid[25, 26] TFCLK HIGH to PTCA Valid[25, 26]
Table 9. OIF-SPI Level 3 Receive System Interface Timing Parameter Values Parameter fRFCLK[21] tRENBS tRENBH tRDATD tRPRTYD RFCLK Frequency RFCLK Duty Cycle RENB Set-up time to RFCLK[23] RENB Hold time to RFCLK [24] RFCLK HIGH to RDAT[31:0] Valid[25, 26] RFCLK HIGH to RPRTY Valid[25, 26] tRFCLKD[21] Description Min. - 40 2 0.5 1.5 1.5 Max. 104 60 - - 6 6 Unit MHz % ns ns ns ns
Notes: 23. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4V point of the input to the 1.4V point of the clock. 24. When a hold time is specified between an input and a clock, the hold time is the time in the nanoseconds from the 1.4V point of the clock to the 1.4V point of the input. 25. Output propagation delay time is the in nanoseconds from the 1.4V point of the reference signal to the 1.4V point of the output. 26. Maximum output propagation delays are measured with 30-pF load on the inputs.
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CONFIDENTIAL
Table 9. OIF-SPI Level 3 Receive System Interface Timing Parameter Values (continued) Parameter tRSOPD tREOPD tRERRD tRMODD tRSXD Parameter fRxClk[21] tRxClkD[21] tRxEnbS tRxEnbH tRxDataO tRxSocO tRxPrtyO tPxClavO Parameter fTxClk
[21]
CY7C9536B
Min. 1.5 1.5 1.2 1.5 1.5 Max. 6 6 6 6 6 Unit ns ns ns ns ns
Description RFCLK HIGH to RSOP Valid RFCLK HIGH to RERR Valid RFCLK HIGH to RSX Valid
[25, 26]
RFCLK HIGH to REOP Valid[25, 26]
[25, 26]
RFCLK HIGH to RMOD[1:0] Valid[25, 26]
[25, 26]
Table 10.UTOPIA Level 3 Receive System Interface Timing Parameter Values Description RxClk Frequency RxClk Duty Cycle RxEnb Set-up Time to RxClk RxEnb Hold Time to RxClk RxClk HIGH to RxData [31:0] Valid RxClk HIGH to RxSoc Valid RxClk HIGH to RxPrty Valid RxClk HIGH to RxClav Valid Min. - 40 2 0.5 - - - - Max. 104 60 - - 6 6 6 6 Unit MHz % ns ns ns ns ns ns
Table 11.UTOPIA Level 3 Transmit System Interface Timing Parameter Values Description TxClk Frequency TxClk Duty Cycle TxEnb Set-up Time to TxClk TxEnb Hold Time to TxClk TxAddr Set-up Time to TxClk TxAddr Hold Time to TxClk TxData [31:0] Set-up Time to TfClk TxData [31:0] Hold Time to TfClk TxPrty Set-up Time to TfClk TxPrty Hold Time to TfClk TxSoc Set-up Time to TfClk TxSoc Hold Time to TfClk TfClk HIGH to PTCA Valid Min. - 40 2 0.5 2 0.5 2 0.5 2 0.5 2 0.5 - Max. 104 60 - - - - - - - - - - 6 Unit MHz % ns ns ns ns ns ns ns ns ns ns ns
tTxClkD[21] tTxEnbS tTxEnbH tTxAddrS tTxxAddrH tTxDataS tTxDataH tTxPrtyS tTxPrtyH tTxSocS tTxSocH tPTCAO Parameter fTCLK[21] tTCLKD[21] tTADDRS tTADDRH tTDATAS tTDATAH tTPARITYS tTPARITYH tTBVALS tTBVALH tTDVALS
Table 12.HBST Transmit System Interface Timing Parameter Values Description TCLK Frequency TCLK Duty Cycle TADDR[3:0] Set-up Time to TCLK TADDR[3:0] Hold Time to TCLK TDATA [31:0] Set-up Time to TCLK TDATA [31:0] Hold Time to TCLK TPARITY Set-up Time to TCLK TPARITY Hold Time to TCLK TBVAL[2:0] Set-up Time to TCLK TBVAL[2:0] Hold Time to TCLK TDVAL_n Set-up Time to TCLK 40 2 0.5 2 0.5 2 0.5 2 0.5 2 Min. Max. 104 60 - - - - - - - - - Unit MHz % ns ns ns ns ns ns ns ns ns
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CONFIDENTIAL
Table 12.HBST Transmit System Interface Timing Parameter Values (continued) Parameter tTDVALH tTSOPS tTSOPH tTEOPS tTEOPH tTERRS tTERRH tTSTFAO tTSOFSTO tTFASTO Parameter fRCLK
[21]
CY7C9536B
Min. 0.5 2 0.5 2 0.5 2 0.5 1.5 1.5 1.5 Max. - - - - - - - 6 6 6 Unit ns ns ns ns ns ns ns ns ns ns
Description TDVAL_n Hold Time to TCLK TSOP Set-up Time to TCLK TSOP Hold Time to TCLK TEOP Set-up Time to TCLK TEOP Hold Time to TCLK TERR Set-up Time to TCLK TERR Hold Time to TCLK TCLK HIGH to TSTFA Valid TCLK HIGH to TSOFST Valid TCLK HIGH to TFAST[3:0] Valid
Table 13.HBST Receive System Interface Timing Parameter Values Description RCLK Frequency RCLK Duty Cycle RREADY_n Set-up Time to RCLK RREADY_n Hold Time to RCLK RCLK HIGH to RDATA[31:0] Valid RCLK HIGH to RADDR[7:0] Valid RCLK HIGH to RPARITY Valid RCLK HIGH to RSOP Valid RCLK HIGH to REOP Valid RCLK HIGH to RERR Valid RCLK HIGH to RBVAL[2:0] Valid RCLK HIGH to RDVAL Valid RCLK HIGH to RSTFA Valid Min. - 40 2 0.5 1.5 1.5 1.5 1.5 1.5 1.2 1.5 1.5 1.5 Max. 104 60 - - 6 6 6 6 6 6 6 6 6 Unit MHz % ns ns ns ns ns ns ns ns ns ns ns
tRCLKD[21] tRREADYS tRREADYD tRDATAO tRADDRO tRPARITYO tRSOPO tREOPO tRERRO tRBVALO tRDVALO tRSTFAO Parameter tCYC[21] tCLKOUTO[22] tCH[21] tCL[21] tCO tDOH tADO tADOH tCENO tCENOH tWEO tWEOH tADVO tADVOH tDS tDH
Table 14.Memory Interface Timing Description CLKOUT Cycle Time CLKOUT Output Delay after SYSCLK CLKOUT HIGH CLKOUT LOW DQ Output Valid after CLKOUT Rise DQ Output Hold after CLKOUT Rise Address Output Delay after CLKOUT Rise Address Output Hold after CLKOUT Rise CEN Output Delay after CLKOUT Rise CEN Output Hold after CLKOUT Rise WE Output Delay after CLKOUT Rise WE Output Hold after CLKOUT Rise ADV/LD Output Delay after CLKOUT Rise ADV/LD Output Hold after CLKOUT Rise DQ Input Set-up before CLKOUT Rise DQ Input Hold after CLKOUT Rise Min. 7.5 - 2.2 2.2 - 0.9 - 0.9 - 0.9 - 0.9 - 0.9 2.8 0.5 Max. - 5 - - 5.5 - 5.5 - 5.5 - 5.5 - 5.5 - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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CONFIDENTIAL
Table 15.CPU System Interface Timing Parameter Values Parameter fSYSCLK[21] tSYSCLKD[21] fCpuClk[21] tCpuAdsS tCpuAdsH tCpuADS tCpuADH tCpuADZ[21] tCpuADO tCpuWrRdS tCpuWrRdH tCpuTaO tCpuBlastS tCpuBlastH tCpuSelS tCpuSelH tCpuIntO Parameter tClk2MHzH[21] tClk2MHzL[21] tClk2MHzR[22] tClk2MHzF[22] tREPW[22] tREO tTOHSDOUTO Parameter tClk16MHzH[21] tClk16MHzL[21] tClk16MHzR[22] tClk16MHzF[22] tRPOHPW[22] tRPOHO tPOHSDOUTO Clk16MHz High Period Clk16MHz Low Period Clk16MHz Rise Time Clk16MHz Fall Time RPOHSTART Pulse Width RPOHSTART Output Delay after Clk16MHZ Rising Edge POHSDOUT Output Delay after Clk16MHZ Rising Edge Clk2MHz High Period Clk2MHz Low Period Clk2MHz Rise Time Clk2MHz Fall Time RE1STROBE or RE2STROBE Pulse Width RE1STROBE or RE2STROBE Output Delay after Clk2MHZ Rising Edge TOHSDOUT Output Delay after Clk2MHZ Rising Edge SYSCLK Frequency SYSCLK Duty Cycle CpuClk Freq. CpuAds_n Set-up Time to CpuClk CpuAds_n Hold Time to CpuClk CpuAD Set-up Time to CpuClk CpuAD Hold Time to CpuClk CpuAD Float CpuAD Output Delay after CpuClk Rise CpuWrRd Set-up Time to CpuClk CpuWrRd Hold Time to CpuClk CpuTa_n Valid Delay CpuBlast_n Set-up to CpuClk CpuBlast_n Hold to CpuClk CpuSel Set-up to CpuClk CpuSel Hold to CpuClk CpuInt Valid Delay Description Min. 133 45 - 7 2 7 2 - - 7 2 - 7 2 7 2 -
CY7C9536B
Max. 133.33[27] 55 66 - - - - 14 10.1 - - 10.1 - - - - 10.1 ns ns ns ns ns ns ns ns Unit MHz % MHz ns ns ns ns ns
Table 16.TOH Serial Interface Receive Timing Parameter Values Description Min. 31 31 - - 62 - - Max. 34 34 6 6 67 8 8 Unit SYSCLK cycles SYSCLK cycles ns ns SYSCLK cycles ns ns
Table 17.POH Serial Interface Receive Timing Parameter Values Description Min. 3 3 - - 7 - - Max. 5 5 6 6 9 8 8 Unit SYSCLK cycles SYSCLK cycles ns ns SYSCLK cycles ns ns
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CONFIDENTIAL
Table 18.TOH Serial Interface Transmit Timing Parameter Values Parameter tClk2MHzH[21] tClk2MHzL[21] tClk2MHzR[22] tClk2MHzF[22] tTEPW[22] tTEO tTOHSDINS tTOHSDINH Clk2MHz High Period Clk2MHz Low Period Clk2MHz Rise Time Clk2MHz Fall Time TE1STROBE or TE2STROBE Pulse Width TE1STROBE or TE2STROBE Output Delay after Clk2MHz Rising Edge Set-up Time of TOHSDIN before the Falling Edge of Clk2 MHz Hold Time of TOHSDIN after the Falling Edge of Clk2 MHz Description Min. 31 31 - - 62 - 50 50
CY7C9536B
Max. 34 34 6 6 67 8 - - Unit SYSCLK cycles SYSCLK cycles ns ns SYSCLK cycles ns ns ns
Table 19.POH Serial Interface Transmit Timing Parameter tClk16MHzH[21] tClk16MHzL[21] tClk16MHzR[22] tClk16MHzF[22] tTPOHPW[22] tTPOHO tPOHSDINS tPOHSDINH Clk16MHz High Period Clk16MHz Low Period Clk16MHz Rise Time Clk16MHz Fall Time TPOHSTART Pulse Width TPOHSTART Output Delay after Rising Edge of Clk16MHz Set-up Time of POHSDIN before Falling Edge of Clk16MHz Hold Time of POHSDIN after Falling Edge of Clk16MHz Description Min. 3 3 - - 7 - 20 20 Max. 5 5 6 6 9 8 - - Unit SYSCLK cycles SYSCLK cycles ns ns SYSCLK cycles ns ns ns
Note: 27. All VC mode configurations require a SYSCLK frequency of 133.33 MHz.
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Switching Waveforms
Line Transmit and Receive Interface Timing
t RXCLKP
CY7C9536B
t
RXCLKH
t
RXCLKL
RXCLK t RXDS RXD[31:0] tRXFPS RXFRAME_PULSE t RXFPH tRXDH
t PARINS SONETRX_PARIN t TXCLKR TXCLKOUT t TXCLKP TXD[31:0]
t PARINH
t TXCLKF
t TXDO
tTXFPO TXFRAME_PULSE t TXFPPW SONETTX_PAROUT t t
PAROUTO
TXCLKIP
TXCLKI
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Switching Waveforms (continued)
Transmit OIF-SPI Level 3 System Interface Timing
CY7C9536B
TFCLK
tTENBS tTENBH
TENB
tTDATS tTDATH
TDAT[31:0]
tTPRTYS tTPRTYH
TPRTY
tTSOPS tTSOPH
TSOP
tTEOPS tTEOPH
TEOP
tTERRS tTERRH
TERR
tTSXS tTSXH tPTADRH
TSX
tPTADRS
PTADR[3:0]
tTMODS tTMODH
TMOD[1:0]
tDTPAO
DTPA[3:0]
tSTPAO
STPA
tPTCAO
PTCA
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Switching Waveforms (continued)
Receive OIF-SPI Level 3 System Interface Timing
CY7C9536B
RFCLK
tRENBS tRENBH
RENB
tRDATO
RDAT[31:0]
tRPRTYO
RPRTY
tRSOPO
RSOP
tREOPO
REOP
tRERRO
RERR
tRVALO
RVAL
tRMODO
RMOD[1:0]
tRSXO
RSX
Transmit UTOPIA Level 3 System Interface Timing
TxClk
tTxEnbS tTxEnbH
TxEnb
tTxAddrS tTxAddrH
TxAddr[4:0]
tTxDataS tTxDataH
TxData[31:0]
tTxPrtyS tTxPrtySH
TxPrty
tTxSocS tTxSocH
TxSoc
tPTCAO
PTCA
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Switching Waveforms (continued)
Receive UTOPIA Level 3 System Interface Timing
CY7C9536B
RxClk
tRxEnbS tRxEnbH
RxEnb
tRxDataO
RxData[31:0]
tRxPrtyO
RxPrty
tRxSocO
RxSoc
tRxClavO
RxClav
Transmit HBST System Interface Timing
TCLK
tTADDRS tTADDRH
TADDR[3:0]
tTDATAS tTDATAH
TDATA[31:0]
tTBVALS tTBVALH
TBVAL[1:0]
tTDVALS tTDVALH
TDVAL_n
tTSOPS tTSOPH
TSOP
tTEOPS tTEOPH
TEOP
tTERRS tTERRH
TERR
tTPARITYS tTPARITYH
TPARITY
tTSTFAO
TSTFA
tTSOFSTO
TSOFST
tTFASTO
TFAST[3:0]
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Switching Waveforms (continued)
Receive HBST System Interface Timing
RCLK
tRREADYS tRREADYH
CY7C9536B
RREADY_n
tRADDRO
RADDR[7:0]
tRDATAO
RDATA[31:0]
tRBVALO
RBVAL[1:0]
tRDVALO
RDVAL
tRSOPO
RSOP
tREOPO
REOP
tRERRO
RERR
tRSTFAO
RSTFA
tRPARITYO
RPARITY
Memory Interface Timing
tCLKOUTO SYSCLK tCYC tCL t CENO CEN t CENOH t AD[18:0] t CLZ DQ1[31:0] & DQ2[31:0] tDS WE t WEOH t ADVO ADV/LD t ADVOH Data In tDH tCO t WEO Data Out t CHZ tDOH
ADOH
CLKOUT
tCH
t ADO
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Switching Waveforms (continued)
CPU System Interface Timing
CY7C9536B
CpuClk
tCpuAdsH
CpuTs_n / CpuAds_n
tCpuAdsS tCpuADZ tCpuADS
CpuAD[31:0] (Input)
tCpuADH
CpuAD[31:0] (Output)
tCpuADO tCpuWrRdH
CpuWrRd
tCpuWrRdS
CpuTa_n
tCpuTaO tCpuBlastH
CpuBlast_n / CpuBdip_n ChipSel
tCpuSelS tCpuIntO
tCpuBlastS
tCpuSelH
CpuInt
Document #: 38-02078 Rev. *G
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CONFIDENTIAL
Switching Waveforms (continued)
TOH Serial Interface Timing
tClk2MHzP
CY7C9536B
Clk2MHz
tClk2MHzR tClk2MHzF
RE1STROBE RE2 STROBE
tREO tREPW tREO
TOHSDOUT
tTOHSDOUTO
TE1STROBE TE2 STROBE
tTEO tTEPW tTEO
TOHSDIN
tTOHDINS tTOHDINH
POH Serial Interface Timing
tClk16MHzP
Clk16MHz
tClk16MHzR tClk16MHzF
RPOHSTART
tRPOHO
POHSDOUT
tRPOHPW
tRPOHSDOUTO
tRPOHO
TPOHSTART
tTPOHO tTPOHPW tTPOHO
POHSDIN
tPOHSDINS tPOHSDINH
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CONFIDENTIAL
Ordering Information
Speed Standard Standard Ordering Code CY7C9536B-BLC CY7C9536B-BLI Package Name 504L2BGA 504L2BGA Package Type 504-pin BGA 504-pin BGA
CY7C9536B
Operating Range Commercial Industrial
Package Diagram
504-Lead L2 Ball Grid Array (37.50 x 37.50 x 1.57 mm) BL504
51-85147-*C
Please see Device Manual and errata document for further details on functional descriptions. POSIC2GVC and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-02078 Rev. *G
Page 45 of 46
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CONFIDENTIAL
Document History Page
Document Title:CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVCTM Document Number: 38-02078 REV. ** *A ECN No. 127207 129314 Issue Date 07/03/03 10/17/03 Orig. of Change QJL CFK New Data Sheet Description of Change
CY7C9536B
Clarified PHY connection in POSIC2GVC logic block diagram Added specification references section Changed note 18 to include STSX-1v Added Single POSIC2GVC APS implementation scheme description Removed statement that pin assignment is tentative Added 16-bit mode operation pin description for TMOD and RMOD Clarified that POSIC_OEn signal tri-states all POSIC2GVC outputs Added that SCAN_ENA should be pulled LOW for normal operation Changed CLK_OUT to CLKOUT in pin assignment table Added parameters PW (total chip power) and Ios (output short circuit current) to DC specifications Changed compatible NoBL part number to CY7C1370B/C Corrected notes for parameters guaranteed by design/char Changed tRERRD/tRERRO parameter minimum from 1.5 ns to 1.2 ns Changed tDOH, tADOH, tCENOH, tWEOH, tADVOH from min 0.5 ns to min 0.9 ns Changed fSYSCLK to max 133.33 MHz Updated package name in ordering information table Removed errata section (reference separate errata document) Changed POSIC2GVCB to POSIC2GVC. Added note to Table 1 (VC bandwidth) and Table 15 (SYSCLK timing parameter) to indicate that all VC mode channel configurations require a SYSCLK frequency of 133.33 MHz Changed data sheet to Final status No document change. Publish first page to web. Removed statement that pinout is tentative in Pin Assignment section Updated Table 6 compatible NoBL SRAM part numbers Removed SDL and HDL spec references throughout document Changed Generic Protocol Encapsulator references through document to GFP encapsulator No content change. Post to web under NDA. Updated Icc3 from 0.26 to 0.75. Updated Icc5 from 0.1 to 0.28. Updated Icc1 from 2 to 1. Updated power from 4.57 to 4.58. Post web under NDA. Changed pin description for OE to note tie to VSS2.
*B
130893
12/24/03
CFK
*C *D
132897 207426
01/26/04 See ECN
CFK CFK
*E *F
215296 318033
See ECN See ECN
PIR QJL
*G
355154
See ECN
QJL
Document #: 38-02078 Rev. *G
Page 46 of 46

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